Field of the Invention
The invention relates to a semiconductor memory having memory banks that can be selected by assigned memory bank decoders.
It is known that memory cells in a semiconductor memory are disposed in a matrix-like manner, that is to say in rows and columns. Respective address decoders are provided for rows and columns and make it possible to select one of the rows or columns, respectively. The memory cells are usually activated in a row-by-row manner via word lines, by access transistors being turned on, via which transistors access is made in each case to a capacitor storing the information of the memory cell. In a column-by-column manner, the conduction path of the transistors is connected to bit lines via which the information of a memory cell can be read out after amplification by a sense amplifier. Access is effected in a corresponding manner when information to be stored is written to the memory cell.
In recent semiconductor memories having dynamic memory cells (DRAMs), the memory cell array has a bank architecture. A memory bank contains all those functional units that are necessary to execute a memory access independently. A memory bank is therefore assigned respective row and column address decoders, and also sense amplifiers and other functional units required for the operation of the semiconductor memory, e.g. timing circuits, redundancy circuits, etc. If appropriate, functional units of different memory banks can be utilized together, for example sense amplifiers or bit line decoders or column decoders.
A memory bank and the functional units assigned to it are activated by memory bank decoders. If a specific memory cell in a memory bank is to be accessed, the functional units assigned to the memory bank are changed over from a standby state to an activated state. This addressing is effected by an output signal, assigned to the memory bank, of the memory bank decoder. Each memory bank has a unique memory bank address assigned to it. If this address is applied to the memory bank decoder, the latter's output signal assigned to the memory bank is activated.
As the number of memory banks increases, the memory bank decoders are becoming more and more complex. For example, a DRAM with a storage capacity of 64 MB contains 16 memory banks, and a DRAM with 128 MB contains 32 memory banks. A single decoder respectively having 16 or 32 output signals for activating a respective memory bank is so complex and requires, on the chip carrying the integrated semiconductor memory, such a large area in the circuitry realization that the regularity of the chip geometry is disturbed.